A design layout generally models a layout comprising one or more devices, such as one or more transistors. Generally a transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate region above the channel regions. The gate region governs current flow within the channel region based upon a voltage or bias applied to the gate region. Generally, when a bias is applied to the gate region such that current flows in the channel region between the source region and the drain region, the transistor is regarded as being on, and when little to no current is flowing in the channel region between the source region and the drain region, the transistor is regarded as being off.